The safe operating area (SOA) of a power semiconductor device is a graphical representation of the maximum operational voltage and current limits of the device subjected to various constraints. The forward bias safe operating area (FBSOA) and the reverse bias safe operating area (RBSOA) represent the device SOA with the gate-emitter forward biased or reverse biased, respectively.
For high voltage devices, the RBSOA becomes more critical due to the low n-base doping levels and associated dynamic avalanche, which will occur at lower current densities. Also, such devices will experience much harsher SOA conditions at high DC link voltages during testing and operation.
Standard planar Insulated-Gate Bipolar Transistor (IGBT) cathode cell designs are normally designed for a high SOA by increasing the latch-up immunity of the n+ source regions. For high voltage IGBTs, this has normally been achieved with the addition of highly doped p+ well regions in the active cell region. However, it is well known that the standard approach mentioned above will not fulfil the SOA requirements especially when designing IGBTs with ratings ranging from 2000 V up to 8000 V. In addition, there is a design trade-off between improved safe operating area using additional p+ well regions and reduced on-state losses for the high voltage IGBT.
U.S. Pat. No. 6,025,622 shows a MOSFET with such a p+ well region in the active cell region. Further p+ guard rings surround the region around the base layers, source layers and the high resistance region under the gate electrode. These p+ guard rings are floating without a contact to the source electrode. They are used as a junction termination to assure high withstand voltage.
As described in EP 0 837 508 A2, for a planar IGBT with low on-state losses, a p doped channel well region is surrounded by an n type layer which acts as a hole barrier region. This will increase the latch-up current during device turn-off. However for high voltage IGBTs with ratings exceeding 2000 V, such an IGBT has shown not to be effective for increasing the SOA capability sufficiently. Such an IGBT planar cell layout and cross section design is shown in FIG. 1.